The present invention relates in general to integrated circuitry and in particular to method and circuitry for implementing programmable on-chip termination resistance with DC voltage level control.
When transmitting signals over distances appreciable with respect to the signal period, mismatches between the impedance of the transmission line and that of the receiver cause signal reflection. The reflected signal interferes with the transmitted signal and causes distortion and degrades the overall signal integrity. To minimize or eliminate the unwanted reflection, transmission lines are resistively terminated by a matching impedance. Conventionally, the input and output pins on an integrated circuit package are terminated by coupling an external termination resistor of, e.g., 50 Ohm value to the relevant pins. For many of today's high speed integrated circuits, and particularly those that have large I/O pin counts, external termination poses a number of problems. At high frequencies, for example, the effects of package parasitics cannot be ignored making the reduction of external terminals (package pins or stubs) desirable. Interconnect paths on a circuit board as well as inside the package contribute to the parasitics increasing the delay in signal propagation. It is desirable therefore to implement the termination resistance on-chip to eliminated some of the parasitics. On-chip termination also reduces the number of external components.
Depending on the circuit application, there are a number of other factors that need to be considered when designing the termination structure. For example, over time, various data signaling techniques have developed to facilitate low voltage high speed signal transmission. Low voltage differential signaling (LVDS), current mode logic (CML), and low voltage pseudo emitter coupled logic (LVPECL) are examples of fully differential signaling techniques, while GTL, SSTL, HSTL are examples of pseudo differential signaling. The signal levels at the interface have not been standardized for every type of signaling technique. For example, LVPECL is a widely used signaling technique that has not been standardized resulting in many different vendor definitions for the signal levels at the interface. An on-chip termination resistance that is optimized for a signaling interface defined by one vendor may not provide optimum termination for another.
Another consideration is the output DC level in systems that use AC coupling at the I/O interface. AC coupling techniques that are typical of high speed communication channels require a biasing network at the receiver to provide a proper DC level for the received signal. For an on-chip differential termination resistance, proper DC biasing is needed.
It is therefore desirable to provide an on-chip termination structure that not only reduces external components and enhances data rate, but that is flexible enough to interface with varying signaling techniques as well as providing appropriate DC biasing when needed.